Double data rate (DDR) dynamic random access memory (DRAM) represent a class of memory integrated circuits used in devices to achieve twice as much bandwidth than preceding single data rate DRAMs. This is accomplished by double pumping (i.e., transferring data on both the rising and falling edges of the clock signal) without increasing an associated clock frequency. Dual in-line memory modules (DIMMs) represent memory modules that comprise a series of dynamic random access memory integrated circuits. DIMMs based on DDR-DRAM have data at double the rate of the clock. This can be achieved by clocking on both the rising and falling edges of the data strobes. Currently, a write transaction to a double data rate (DDR) dual in-line memory module (i.e., DDR DIMM)) expects all data drivers to transmit during a write operation. During such write operations, all transmitters (i.e., data drivers) are active even though not all data drivers are used during such operations. As such, write transactions to DDR DIMMs expect all data drivers to transmit, and thus, unnecessarily consume power. This leads to power being wasted, which is a critical problem in today's integrated circuits and devices.
Moreover, current low-power DDR designs may not have termination associated with the DDR receivers. Such DDR designs still send data bits even though such data bits are masked and not stored by memory. However, some graphics DDR (GDDR) are configured with termination having a pull-up to power at the receiver side. These GDDR devices usually have all data drivers on during a write operation. In GDDR devices, if the receive termination is configured with only a pull up (or only a pull down), then having the driver on while driving 1 (or 0 in the case of pull down) results in no power being consumed because the driver and the termination are being pulled in the same direction. In such GDDR devices, it is also possible to tristate (i.e., turn off) the data driver rather than drive 1 in the event of power pull-up termination, or drive 0 in the event of ground pull-down termination for GDDR. Thus, for GDDR devices having termination to power, driving 1 can result in zero I/O power consumption. However, with respect to DDR devices, such an approach of driving 1s when the DDR receivers are terminated to power does not result in zero power consumption for such DDR devices.
Because many devices that utilize DDR memories are battery powered, it is desirable, among other things, to more efficiently reduce power consumption in order to, for example, increase the battery life of such devices.